FIG. 12 is a simplified diagram showing a conventional RF circuit utilized in handsets and other wireless devices including a solid state RF switch that passes received RF signals at a frequency f2 from an antenna to a receiver circuit via a low noise amplifier (LNA) circuit (not shown), and also passes signals at a frequency f1 from a transmitter via a power amplifier (PA) circuit (not shown) to the antenna. Because solid state RF switches are not perfectly linear, intermodulation (frequency mixing) of the two frequency components f1 and f2 generates false signals f3 that are passed via the main signal line to the receiver circuit. The false signals f3 are typically generated at harmonic frequencies (i.e., integer multiples of the source frequencies, such as 2*f1), but may also be generated at sum and difference frequencies (e.g., such as 2*f1−f2). These false signals can manifest themselves as noise on allowed communication bands. Third-order harmonic intermodulation products are a particular issue for new proposed carrier aggregation uplink standards. For example, future carrier aggregation implementations require that inputs of 25 dBm (316 mW) generate less than −110 dBm (8 fW) at mixing frequencies.
Various conventional harmonic suppression techniques, such as the use of diplexers connected at the antenna port and better isolation between the transmission and receiver signal paths, can be used to mitigate the linearity issues associated with the use of solid state RF switches, but these conventional approaches incur associated cost and performance penalties.
A conventional series-type harmonic cancellation technique is taught in U.S. Pub. App. No. 2014/0335801 A1, which discloses a harmonic cancellation device formed by standard circuit elements placed in series with the series branch of a solid-state RF switch. There are at least two problems associated with this series-type approach. First, the on-state series switch branch has very low voltage across it (e.g., a typical GSM-capable switch branch, realized in a monolithic silicon technology, with 24 dBm input power would have only around 140 mV across it). As a result, to achieve significant current through the series-type harmonic cancellation device, the device must be configured to exhibit relatively low impedance, which requires the use of relatively large device sizes that significantly increase the resulting size of the host RF circuit. Fundamentally, harmonic distortion can also be improved by reducing the on-state resistance of the switch's series branch, but this makes even less voltage headroom available for the series-type harmonic cancellation device. Second, such series-type harmonic cancellation devices will be subjected to the full voltage generated across the off-state series switch branch, which can be very high (i.e., 40-70V) under mismatch (e.g., high Voltage Standing Wave Ration (VSWR)) conditions. Most individual circuit elements in RF switch silicon technology cannot withstand such voltages, so protection devices (e.g., stacks of many FETs) must be placed in series with the series-type harmonic cancellation device. Some of the already-small on-state voltage is dropped across these protection devices, making implementation even more challenging.
What is needed is a harmonic cancellation technique for RF circuits that overcomes the deficiencies of conventional approaches set forth above. In particular, what is needed is a harmonic cancellation device that facilitates the transmission of higher RF signal voltages on a main signal line, allows the use of smaller, high impedance devices that take less chip area and have less impact on the core RF switch performance, and is not adversely affected by Ron reduction.